Design of an ASIC model in SDL

The HdS (hardware dependent Software) department of A1catel Bell Antwerp, part of the Carrier Data division is responsible for the design of embedded software, firmware and off-line test software towards verification and test of ASICs, PCB-boards and complete systems. The HdS designers are interested in an executable hardware model of the system to be designed as a virtual target for debugging the HdS verification software. The model should have the capability to be interfaced with the HdS verification software, implemented in C, so that validation and co-verification of the SWIHW system can be performed during the top-level design phase. This model can also be used by the ASIC-designers as a reference model and for early validation of the architecture decisions in the design trajectory. Starting from an ASIC specification, it is important to investigate what abstraction level is needed to satisfy both ASIC and HdS engineers. Quantitative information, about the effort required for designing a HW model has been also connected. This information will be indispensable for management planning in case HW modeling will be introduced in the design flow. The results of this project can be used as a basis for further development of a co-design methodology. The ASIC will be modeled in SDL. SDL was originally developed for the specification and description of communicating systems consisting of hardware and software, however SDL is currently mainly used in the software design process only. In this thesis, a part of the MTM (Multi Path Self-Routing Traffic Manager) ASIC is modeled in SDL. Through simulation, the model is validated and verified. After that, the possibilities are studied to integrate the HdS verification SW with the HW model for coverification purposes.